Apparatus for postponing processing of interrupts by a microprocessor
US6192441A · kind A · utility
3Cited by
13References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1996 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Aug 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.