Apparatus and method for optimizing performance of a cache memory in a data processing system
US6192449A · kind A · utility
5Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1996 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Apr 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15). If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.