Data processing with progressive, adaptive, CPU-driven power management
US6192479A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1995 |
| Grant date | Feb 20, 2001 |
| Priority date | — |
| Expiry date | Jan 19, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The power consumption of a single chip data processing device (21) is controlled. An activity meter (53) signals the activity level of at least one functional unit (FU). A clock arbiter (51) has three states: an up state; a hold state; and a down state. The clock arbiter progresses from the up state to the hold state and from the hold state to the down state when the activity level is below a predetermined activity threshold. The clock arbiter progresses from the down state to the hold state and from the hold state to the up state when the activity level is above the predetermined activity threshold. A clock generating circuit (43, 45, 47) supplies a clock signal periodically increasing in frequency responsive to the up state, unchanging in frequency responsive to the hold state and periodically decreasing in frequency responsive to the down state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.