Method of assembly stress protection
US6194249A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Nov 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention offers a solution to several problems associated wit IC packages that use a top layer of molded plastic. This has been achieved by inter-posing a dummy layer of dielectric material between the upper surface of the integrated circuit wafer and the molded plastic layer. This dummy layer is patterned and etched so that its surface becomes an alternating series of valleys and ridges, care being taken to ensure that all wiring lines are protected by being within ridges. This structure serves both to protect the wiring lines during the application of the molded plastic and, because of the large surface area of contact between plastic and wafer, excellent adhesion of the molded plastic to the wafer is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.