Method for fabricating CMOS device
US6194256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
Disclosed is a method for fabricating CMOS device using a SOI substrate, and more particularly the method for fabricating CMOS device capable of improving mobility of electron and hole. The present invention provides a method for fabricating CMOS device comprising the steps of: providing an SOI substrate having a stacking structure of a base layer, a buried oxide layer and a semiconductor layer, wherein the SOI substrate is divided into a first region where a PMOS is formed later and a second region where an NMOS is formed later; forming first field oxide films to be contacted with the buried oxide layer by applying a thermal oxidation to a selected portion of the semiconductor layer being disposed in the first region of the SOI substrate; forming trenches with a depth to be contacted with the buried oxide layer in a selected portion of the semiconductor layer being disposed in the second region of the SOI substrate and then forming second field oxide films by filling the trenches with an insulating layer; and forming the PMOS in the portion of the semiconductor layer being defined by those first field oxide films, and the NMOS in the portion of the semiconductor layer being define…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.