Method of manufacturing the floating gate of split-gate flash memory
US6194300A · kind A · utility
8Cited by
11References
11Claims
0Family size
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Key dates
| Filing date | Jul 5, 2000 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jul 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for fabricating the floating gate of a split-gate flash memory. A patterned sacrificial layer is formed over a substrate. A doped polysilicon layer and an insulation layer are formed in sequence over the sacrificial layer. The doped polysilicon layer and the insulation layer above the sacrificial layer are removed by chemical-mechanical polishing. The exposed doped polysilicon layer is removed. Finally, the sacrificial layer is removed to complete the fabrication of the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.