DLL circuit
US6194930A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock. The DLL circuit comprises a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phases of the first clock against that of a second clock, generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal. The delay control circuit generates a single delay control signal, which changes by a minimum delay quantity unit a delay quantity of the variable delay circuit in a first operating period of the DLL circuit, and generates a binary delay control signal, which changes by a binary unit a delay quantity of the variable delay circuit in a second operating period that differs from the first operating period of the DLL circuit. A lock-on state can be achieved in a short time, and stable operation is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.