Method and an auxiliary circuit for preventing the triggering of a parasitic transistor in an output stage of an electronic circuit
US6194948A · kind A · utility
9Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.