Content addressable memory cells and words
US6195278A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modifications to CAM cell designs are required as supply voltages utilized decrease. In one possible modified design, when a reference bit applied to the CAM cell matches a stored bit, p-channel pass transistors within the CAM cell can pass a full logical high to an n-channel chain transistor coupled within a NAND configuration with other CAM cells. This full logical high can result in increased transition speed, a decrease in degradation, and/or a decrease in power dissipation for the n-channel chain transistor. Further, compared to using n-channel pass transistors, the use of p-channel pass transistors to transfer the logical high voltage can increase the transition speed, decrease the degradation, and/or decrease the power dissipation for the pass transistors. Alternatively, the use of n-channel pass transistors and a p-channel chain transistor can gain similar advantages if the logic was opposite.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.