Semiconductor memory device and its refresh address signal generating method adapted to reduce power consumption during refresh operation
US6195304A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2000 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Feb 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the capacitive loads including a smallest capacitive load and a largest capacitive load. A refresh address counter outputs a number of bit signals which constitute a refresh address signal, the refresh address signal indicating an address of a memory cell to be refreshed in the memory device, the bit signals having predetermined high/low-state change periods which are different from each other, the bit signals including a first bit signal corresponding to the smallest capacitive load and a second bit signal corresponding to the largest capacitive load. A selector is provided to connect the refresh address counter outputs to the memory cell array, and assigns the predetermined high/low-state change periods for the respective bit signals of the refresh address signal in accordance with a correspondence between the bit signals and the capacitive loads. A refresh address signal generating method is also disclosed for use in the semiconduct…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.