Method and system for selectively disabling simulation model instrumentation
US6195629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Nov 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation of a digital circuit design. According to the present invention, an instrumentation entity, described utilizing a hardware description language to include an output signal to indicate an occurrence of an event during simulation, is implemented into a simulation model of a digital circuit design. Next, the output signal is associated with a unique output storage element. Finally, a disable mechanism uniquely associated with said output signal is provided, such that the output signal may be selectively masked by disabling the storage element during simulation testing of the digital circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.