Combined associative processor and random access memory architecture
US6195738A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/955
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the associative processor memory array while storing temporary results and parameters in the random access memory for a fully programmable, low-cost die suitable for consumer electronics applications. Parallel communication between thousands of memory words in the associative memory array and the random access memory is provided via logic hardware operative as source and destination for associative search and modify (compare and write) processing operations and also operative to read and write thousands of data elements from and to the random access memory. The tags register also serves as a communication bus for parallel communication between associative memory words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.