Method and apparatus for passing data among processor complex stages of a pipelined processing engine
US6195739A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient "context" data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.