Method and apparatus for tolerating power outages of variable duration in a multi-processor system
US6195754A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1997 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jan 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for tolerating failure of the AC power source in a power supply switchable between the AC power source and a battery, in a processor system having a set of one or more components subject to being powered down. When the failure of the AC power source is recognized, the power supply is switched from the AC power source to the battery. For a first period of time, the battery powers the processor system with all components powered on. The battery then powers the processor system with the specific set of components powered off for a second period of time. In one embodiment, a determination is made that the battery can power the processor system with the set of components powered down for a predetermined period of time. A determination of the first period of time is then made as the capacity of the battery exceeding the predetermined period of time, if the excess capacity is used to power the processor system with the set of components powered on. In effect, a processor system incorporating one embodiment of the invention rides through a first period of a power outage, operating as normal and masking the loss of AC power. For a second, predetermined period, the pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.