Method for supporting 11/2 cycle data paths via PLL based clock system
US6195757A · kind A · utility
1Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1998 |
| Grant date | Feb 27, 2001 |
| Priority date | — |
| Expiry date | Jan 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for improving system cycle time while supporting 11/2 cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a first chip and a memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.