Method of fabricating a thin film transistor
US6197625A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6715
Abstract
A method of fabricating a thin film transistor having a vertical offset layer which prevents the damage on an active layer due to the etching plasma by preserving the vertical offset layer during an etching process for separating an ohmic contact layer. The method includes forming a gate electrode on an insulating substrate, forming a first insulating layer on the gate electrode and an exposed surface of the insulating substrate, forming an active layer on the first insulating layer, forming successively an amorphous silicon layer and a heavily-doped amorphous silicon layer on the entire surface including the active layer, forming a vertical offset layer and an ohmic contact layer by simultaneously patterning the /heavily-doped amorphous silicon layer and the amorphous silicon layer, forming a source electrode and a drain electrode connected to the ohmic contact layer, and removing an exposed portion of the ohmic contact layer by etching the ohmic contact layer using the source electrode and the drain electrode as etch masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.