Process for fabricating vertical transistors
US6197641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Jun 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
Abstract
A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconduc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.