Sample and hold circuit and method therefor
US6198314A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Jan 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit (200) accepts an input (202). During a first half of the clock (204) (either an active high portion or an active low portion) the devices (216, 220, and 222) drive the node (218) to a voltage representative of the voltage present on input (202). At a rising edge of the clock (204), the switch (222) is disabled and the voltage on the node (218) is forced to a higher hold voltage by a capacitor (224). While sample circuit (208) is holding the high voltage on node (218), a hold circuit (210) is settling to a hold voltage representative of the voltage on node (218) in a master-slave fashion. This manner of clocking and controlling the circuit (200) allows circuit (200) to be used in low power, high speed telecommunications systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.