Duty-ratio correction circuit and clock generation circuit
US6198322A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 9, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Feb 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty ratio can be corrected to 1:1 without affecting the operation of a PLL or DLL circuit. A rising-edge control circuit (1a) generates a signal (S10) by inverting a signal (S6), and varies a time required for a high to low transition of the signal (S10). A comparator (A1) causes a transition of a signal (S2) when the signal (S10) becomes less than a reference value (Vref), so the duty ratio of the signal (S2) varies according to the length of its fall time. A duty-ratio detecting circuit (2) is a charge pump for drawing or passing a constant amount of current according to a voltage of the signal (S2). A duty-ratio correction filter (3) converts a signal (S8) obtained from the duty-ratio detecting circuit (2) into a smooth voltage signal (S9). This signal (S9) becomes a feedback signal to the rising-edge control circuit (1a) for correcting the duty ratio of the signal (S2) to 1:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.