CMOS circuit
US6198334A · kind A · utility
42Cited by
7References
3Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Apr 24, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Apr 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a CMOS noise eliminating circuit, a plurality of PMOS transistors or NMOS transistors are connected in series so as to cause of switching speeds or switching timings of the PMOS transistors or the NMOS transistors, which are connected in series, to differ from each other, thereby improving the noise-resistant performance of a semiconductor integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.