Patent · US Expired

Dual edge-triggered phase detector and phase locked loop using same

US6198355A · kind A · utility

25Cited by
12References
9Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 12, 1999
Grant dateMar 6, 2001
Priority date
Expiry dateMar 12, 2019

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/0898
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

There is disclosed a phase detector which triggers on both rising and falling edges of an input pulse signal. This effectively doubles the frequency of the input signal. When the phase detector is used in a phase locked loop, the doubled frequency means that a lower division ratio can be used, thereby reducing any noise contribution introduced thereby.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.