Neural-flash analog-to-digital converter using weighted current similation
US6198421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/36
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a flash analog-to-digital converter (ADC) based on a feedforward perceptron. The ADC includes a plurality of N stages to provide N digital signals. The plurality of N stages includes a first stage to provide a sum of an input current, related to a voltage to be converted, and of a reference current. The first stage provides a first digital signal in one of first and second states if the sum has one of first and second signs, respectively. The plurality of N stages further includes i stages, with i=2 . . . N. Each stage i includes an output circuit and 2.sup.(i-2) sub-stages coupled to the output circuit. Each sub-stage includes an input and a hidden circuit coupled therebetween. The input circuit is configured to provide a first sum of the input current and of a first reference current. Each hidden circuit provides to the output circuit a second reference current when the first sum has a first sign. The output circuit generates an i.sup.th digital signal in one of a first and second states when a second sum of the input current and of the second reference current has one of first and second signs respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.