Semiconductor memory device with hierarchical bit line architecture
US6198648A · kind A · utility
2Cited by
1References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 29, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Nov 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, a plurality of decoders for selectively activating the plurality of word lines in accordance with an address, and a plurality of banks arranged in a predetermined direction. Each of the plurality of banks is connected to at least one of the plurality of word lines. At least two of the plurality of word lines are connected to one common decoder of the plurality of decoders. Each of at least two of the banks is connected to the at least two word lines of the plurality of word lines. The at least two banks are not adjacent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.