High density flash memory architecture with columnar substrate coding
US6198658A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1999 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Oct 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.