Memory device having row decoder
US6198686A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2000 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Jul 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.