High speed dynamic chaining of DMA operations without suspending a DMA controller or incurring race conditions
US6199121A · kind A · utility
28Cited by
10References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for dynamic chaining of DMA operations that includes a count to keep track of control blocks associated with such operations when appended to a current chain of control blocks. The count is checked by a DMA controller upon completing the data-transfer operation associated with each block or each control-block chain depending on the use of a wait bit. Memory used to hold control blocks may be preallocated with anticipated control blocks associated in a predefined linked list to avoid the need for subsequently updating existing control blocks when new blocks are appended to a chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.