System for explicitly referencing a register for its current content when performing processor context switch
US6199156A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.