Time-lag duplexing techniques
US6199171A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1691
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and implementing system are provided for handling detected faults in a processor to improve reliability of a computer system. An exemplary fault-tolerant on-line transactional (OLT) computer system is illustrated which includes first and second OLT processors connected to an I/O processor through a system bus. Transaction results are stored in local processor buffers and at predetermined batch intervals, the stored transactions are compared. The matched transaction results are flushed to data store while unmatched transactions are re-executed. If the same errors do not occur during a re-execution, the errors are determined to be transient and the transaction results are flushed to storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.