Method of manufacturing semiconductor device having capacitor contact holes
US6200853A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Oct 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having capacitor contact holes. The method comprises: forming a first insulating film to cover the gate electrode and the source/drain electrodes; forming a second insulating film on the first insulating film; forming a third insulating film made of material different from that of the second insulating film on the second insulating film; forming a first resist film on the third insulating film; patterning the first resist film by using a first exposure mask to form a patterned first resist film; selectively removing the third insulating film by using the patterned first resist film as a mask; forming a second resist film to cover the patterned first resist film; patterning the second resist film by using a second exposure mask to form a patterned second resist film; selectively removing the first and second insulating films on at least a portion of one of the source/drain regions in each of the element forming regions by using the patterned first and second resist films as a mask to form capacitor contact holes; and forming a conductive film to fill the capacitor contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.