Using epitaxially grown wells for reducing junction capacitances
US6200879A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1998 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Dec 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.