Semiconductor chip having a low-noise ground line
US6201308A · kind A · utility
5Cited by
1References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1998 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip has a first ground line for maintaining a stable ground potential for the internal circuit. The first ground line is connected to a second ground line disposed on a scribe region of the semiconductor chip via a bonding pad, which is connected to an external lead frame. I/O circuit has a third ground line directly connected to the second ground line without passing the bonding pad. The noise propagated from the third ground line to the first ground line is reduced by passing the noise through the bonding pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.