Field effect transistor logic circuit with reduced power consumption
US6201416A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Mar 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018535
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed a field effect transistor logic circuit having an output terminal to be connected to a gate of an input field effect transistor in a next stage field effect transistor logic circuit. The field effect transistor logic circuit includes a depletion transistor having a drain connected to a first power supply voltage, an enhancement transistor having a drain connected at a node in common to a gate and a source of the depletion transistor. A gate of the enhancement transistor is connected to an input terminal, and a source of the enhancement transistor is connected to a second power supply voltage which is lower than the first power supply voltage. A high level potential limiting circuit is connected between the node and the output terminal, to lower a potential of the output terminal to a level which turns on a drain-source channel of the input field effect transistor of the next stage field effect transistor logic circuit but which never turns on a gate-source of the input field effect transistor of the next stage field effect transistor logic circuit, when the potential of the node is at a high level. A lower level lowering circuit having an input connected to the i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.