Divided reset for addressing spatial light modulator
US6201521A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1996 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Sep 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/061
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of implementing pulse-width modulation in a display system (10, 20) that uses a spatial light modulator (SLM) (15). Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each display element of the SLM and representing a bit weight of the intensity value to be displayed by the display elements. Each bit-plane has a display time corresponding to a portion of the frame period, with bit-planes of more significant bits having longer portions. The SLM is divided into reset groups connected to different reset lines (34), so that one reset group can be loaded and its display time begun while the next reset group is loaded. (FIG. 3). Short bit-planes are possible because the display time need not include the time to load the entire array, and for any reset group, its reset can be delayed while other reset groups are loaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.