Electronic memory with disturb prevention function
US6201731A · kind A · utility
46Cited by
8References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.