Semiconductor memory device with redundant row substitution architecture and a method of driving a row thereof
US6201745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2000 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Apr 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a sub word line driver structure and includes a main word line decoder driver, an address programming circuit, and a redundant main word line decoder driver. When row address bit signals are input, the main word line decoder driver drives a main word line corresponding to the row address bit signals regardless of a row replacement with redundant rows. If the row address bit signals correspond to programmed defective row address bit signals, the address programming circuit generates a redundant row select signal, in response to which the activated main word line is deactivated and a redundant main word line is activated. According to the redundant row replacement scheme of the present invention, access time is reduced without an increase of a layout area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.