Self-timed memory reset circuitry
US6201757A · kind A · utility
26Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1999 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Aug 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory timing architecture which very accurately tracks the read and write timing of a memory over a wide range of array sizes, with separate read and write timing circuits. The read reset circuitry uses a plurality of dummy cells to gauge the time necessary to complete the read operation, while the write reset uses a single dummy cell to gauge the time necessary to complete the write operation. These circuits provide for a more accurately-timed feedback signal, which allows for increased speed while at the same time reducing power consumption and heat buildup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.