Packet delay estimation in high speed packet switches
US6201793A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1998 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Mar 16, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An improved packet delay estimation method results from an indirect measurement method that employs an estimation method based on sampled lengths of queues and measured traffic. A complex system of queues sharing the same constant rate server and driven by a non-trivial scheduling scheme is split into logical clusters of queues. The method estimates packet delay based on a two-level approximation. On the first level of approximation, effects of the fact that the server is shared by other clusters is approximated by an equivalent reduction of the service rate. On the second level of approximation, individual queue lengths within a cluster are sampled and, based on the knowledge of the scheduling discipline, used to obtain the upper and lower bounds on the occupancy of the equivalent FIFO buffer. Estimate of the delay is found based on the effective buffer occupancy, and the effective service capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.