State machine with a dynamic clock gating function
US6202166A · kind A · utility
4Cited by
5References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 5, 1998 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Nov 5, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state machine with a dynamic clock gating function according to the invention is disclosed. In the state machine, a gating clock control logic is used to gate a clock signal input to flip-flops which do not need a clock sample input. Accordingly, the total capacitance of capacitors which are charged/discharged following the state transition of a clock signal is greatly reduced, thereby decreasing the power consumption of the state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.