Method for identifying and correcting errors in a central processing unit
US6202174A · kind A · utility
Inventors
Key dates
| Filing date | Sep 16, 1996 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Sep 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions. For proactive debugging, the CPU compares instructions to be executed with each of the known-to-be-erroneous instructions, and on finding a match, injects the corresponding fix instructions into the to-be-executed instructions. Therefore, known errors e.g. the PENTIUM arit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.