Method for diagnosing bridging faults in integrated circuits
US6202181A · kind A · utility
28Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1997 |
| Grant date | Mar 13, 2001 |
| Priority date | — |
| Expiry date | Nov 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for diagnosing bridging faults with inexpensively-obtained stuck-at signatures, in which only those faults determined to be realistic through inductive fault analysis are considered as candidates, match restrictions and match requirements are imposed during matching in order to minimize diagnosis size, and match ranking is applied and the matching criteria relaxed to further increase the effective precision and to increase the number of correct diagnoses. In addition, the method reduces the number of bridging fault candidates by constructing a dictionary of composite signatures of node pairs based on a ranking threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.