Manufacturing method for a capacitor in an integrated memory circuit

US6204119A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Gerrit Lange · Denzlingen, DE
• Martin Franosch · Munich, DE
• Wolfgang Hönlein · Unterhaching, DE
• Volker Lehmann · Hersbruck, DE
• Hans Reisinger · Grünwald, DE
• Herbert Schafer · Höhenkirchen-Siegertsbrunn, DE
• Reinhard Stengl · Stadtbergen, DE
• Hermann Wendt · Grasbrunn, DE

Key dates

• Filing date: May 14, 1999
• Grant date: Mar 20, 2001
• Expiry date: May 14, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/97

Abstract

A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p.sup.+ /p.sup.- silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.