Filamentary electron-emission device having self-aligned gate or/and lower conductive/resistive region
US6204596A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/298
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electron-emitting device contains a lower conductive region (22), a porous insulating layer (24A, 24B, 24D, 24E, or 24F) overlying the lower conductive region, and a multiplicity of electron-emissive elements (30, 30A, or 30B) situated in pores (28.sub.1) extending through the porous layer. The pores are situated at locations substantially random relative to one another. The lower conductive region typically contains a highly conductive portion (22A) and an overlying highly resistive portion (22B). Alternatively or additionally, a patterned gate layer (34B, 40B, or 46B) overlies the porous layer. Openings (36, 42, or 54.sub.1) corresponding to the filaments extend through the gate layer at locations generally centered on the filaments such that the filaments are separated from the gate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.