Destructive read type memory circuit, restoring circuit for the same and sense amplifier
US6205076A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.