Address generating circuit of semiconductor memory device
US6205081A · kind A · utility
5Cited by
2References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address generating circuit of a semiconductor memory device includes address buffers, multiplexers, shift registers and latches by which high-bit and low-bit write/read addresses in a normal mode and in a burst mode are routed through separate paths. A control circuit routes the high-bit read address data through a different path than the high bit write address data. The paths are joined to a common output latch, and include differential delays for the data. Similarly, the low-bit read continuing burst address data is routed through a different path than the low bit continuing burst write address data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.