System and method for floating-computation for numbers in delimited floating point representation
US6205460A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2000 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | May 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Floating point numbers and other values are represented in a "delimited" representation in which all numbers, including those which would in the IEEE Std. 754 representation, be in the de-normalized format, are in a format which is normalized with an implicit most significant digit having the value "one." For numbers which would, in the IEEE Std. 754 representation, be in the de-normalized format, in the delimited representation. PA1 (i) all of the bits of the exponent field have the value "zero," PA1 (ii) the bits in the fraction field correspond to the bits in the fraction field of the de-normalized format shifted to the left a number of times corresponding to one more than the leading zeros in the fraction field of the de-normalized format thereby to provide the implicit most significant digit with the value "one," and PA1 (iii) a delimiter flag is provided in the bit position of the fraction field to the right of the bit which corresponds to the least significant bit in the fraction field of the de-normalized format, thereby to indicate the series of bits in the fraction field of the delimited representation which correspond to the series of bits immediately to the right of the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.