Device and method for controlling data storage device in data processing system
US6205516A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 1998 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Nov 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mode register setting region for SDRAM is provided on a memory map. In order to set the mode register with a desired operation mode, a CPU executes a writing operation to write a command content to this mode register setting region. In other words, the CPU outputs address data for that region and I/O data indicative of the desired command content. A control signal generating circuit receives this address data, and judges whether or not this address data is for the mode register setting region. When the control signal generating circuit determines that this address data is for the mode register setting region, the control signal generating circuit outputs a selection signal to the selection circuit. Upon receipt of the selection signal, the selection circuit generates specific address data, to be set to the mode register, based on the I/O data that has been inputted together with the original address data and that has been written in a region indicated by the address data. The selection circuit outputs the specific address data to the internal RAM. The mode register in the RAM is thus set with the content of the desired mode indicated by the specific address data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.