Method and apparatus for implementing non-temporal stores
US6205520A · kind A · utility
23Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.