Processor with enhanced instruction set
US6205540A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The number of opcode functions exceeds the number of opcodes available by virtue of a technique employing dual function opcodes wherein the second function is executed when a particular resolving flag is put into a set state and otherwise the first function is executed. Furthermore, a generic push opcode and a generic pop opcode are employed without any register pointer designations so that a series of push operations can be performed using a single opcode and a series of pop operations can be performed using a single opcode. The utility of the processor is further enhanced by incorporating a series of handler opcodes that permits simulating on the instruction set of the processor a program designed for a different instruction set. A special simulator opcode called a jump vector opcode is employed to control the operation of reading in the target opcode, applying an algorithm that provides the host processor address for corresponding handler opcodes and jumping to those addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.