Computer system having a multi-pointer branch instruction and method
US6205546A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1999 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Mar 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer and a method are described having multiple pointers for a branch instruction. A branch target instruction called by the branch instruction is divided into H parts locatable by K pointers. L of the K pointers are stored in the branch instruction and K-L pointers are stored with the H parts of the branch target instruction. A tag identifies a variable boundary between first and second halves of the memory, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space are compressed and decompressed in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.