Tamper resistant methods and apparatus
US6205550A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1997 |
| Grant date | Mar 20, 2001 |
| Priority date | — |
| Expiry date | Sep 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one apparatus, a number of obfuscated programming instructions are equipped to self-verify whether execution of the obfuscated programming instructions is being observed. In another apparatus, a number of obfuscated programming instruction are equipped to determine whether the apparatus is being operated in a mode that supports single step execution of the obfuscated programming instructions. In yet another apparatus, a number of obfuscated programming instruction are equipped to verify whether an amount of elapsed execution time has exceeded a threshold. In yet another apparatus, a first and a second group of obfuscated programming instruction are provided to implement a first and a second tamper resistant technique respectively, with the first and the second group of programming instructions sharing a storage location for a first and a second key value corresponding to the first and the second tamper resistant technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.